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? semiconductor components industries, llc, 2011 july, 2011 ? rev. 6 1 publication order number: NCP370/d NCP370 positive and negative overvoltage protection with internal low r on n-mosfets and reverse charge control pin the NCP370 is an overvoltage, overcurrent and reverse control device. two main modes are available by setting logic pins. first mode is direct mode from wall ? adapter to the system. in this mode the system is both positive and negative over ? voltage protected up to +28 v and down to ? 28 v. the wall adapter (or ac/dc charger) is disconnected from the system if the input voltage exceeds the overvoltage (ovlo) or undervoltage (uvlo) thresholds. at power up, the v out turns on 30 ms after the v in exceeds the undervoltage threshold. the second mode (see tables 1 & 2), called the reverse mode, allows an external accessory to be powered by the system battery or boost converter. here the external accessory would be connected to the device input (bottom connector of system) and the device battery would be at the device output. in this case overcurrent protection is activated to prevent accessory faults and battery discharge. thanks to the NCP370 using an internal nmos, the system cost and the pcb area of the application board are minimized. the NCP370 provides a negative going flag (flag ) output which alerts the system that a fault has occurred. in addition, the device has esd ? protected input (15 kv air) when bypassed with a 1 f or larger capacitor. features ? overvoltage protection up to 28 v ? negative voltage protection down to ? 28 v ? reverse charge control: rev ? direct charge control: dir ? overcurrent protection ? thermal shutdown ? on ? chip low r ds(on) nmos transistors: typical 130 m ? overvoltage lockout (ovlo) ? undervoltage lockout (uvlo) ? soft ? start ? alert flag output ? compliance to iec61000 ? 4 ? 2 (level 4) 8 kv (contact) 15 kv (air) ? esd ratings: machine model = b human body model = 2 ? 12 lead tllga 3x3 mm package ? this is a pb ? free device typical applications ? cell phones ? camera phones ? digital still cameras ? personal digital applications ? mp3 players marking diagram a = assembly location l = wafer lot y = year w = work week = pb ? free package http://onsemi.com 12 pin llga mu suffix case 513ak nc out flag dir rev ilim in in gnd res res res NCP370 (top view) 12 11 10 9 8 7 1 2 3 4 5 6 ncai 370 alyw (note: microdot may be in either location) 1 device package shipping ? ordering information NCP370muaitxg llga12 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
NCP370 http://onsemi.com 2 10k 1 f 4.7 f li+battery gnd wall adapter NCP370 1 2 3 8 9 10 7 11 12 figure 1. typical application circuit in in gnd ilim out nc r limit flag rev charger system rev dir dir flag rev dir flag res res res 4 5 6 functional block diagram figure 2. functional block diagram gate driver and reverse ocp logic charge pump control logic and timer uvlo ovlo thermal shutdown en block vref input dir gnd flag rev i lim output
NCP370 http://onsemi.com 3 pin function description pin name type description 1, 2 in power input voltage pins. these pins are connected to the power supply. a 1 f low esr ceramic capacitor, or larger, must be connected between these pins and gnd. the two in pins must be hardwired to common supply. 3 gnd power main ground 4 res input reserved pin. this pin must be connected to gnd. 5 res input reserved pin. this pin must be connected to gnd. 6 res input reserved pin. this pin must be connected to gnd. 7 ilim output current limit pin. this pin provides the reference, based on the internal band ? gap voltage reference, to limit the over current, across internal n ? mosfets, from battery to external accessory. a 1% tolerance, or better, resistor shall be used to get the highest accuracy of the overcurrent limit. 8 rev input reverse charge control pin. in combination with dir , the internal n ? mosfets are turned on if battery is applied on the out pin (see tables 1 & 2). in reverse mode, the internal overcurrent protection is activated. when reverse mode is disabled, the NCP370 current consumption, into out pin, is drastically decreased to limit battery discharge. 9 dir input direct mode pin. in combination with rev , the internal n ? mosfets are turned on if a wall adapter ac ? dc is applied on the in pins (see tables 1 & 2). the device enters in shutdown mode when this pin is tied to a high level and the rev pin is tied to high. in this case the output is disconnected from input. the state of this pin does not have an impact on the fault detect of the flag pin. 10 flag output fault indication pin. this pin allows an external system to detect fault condition. the pin goes low when input voltage exceeds ovlo threshold or drops below uvlo threshold, charge current from battery to accessory exceeds current limit or internal temperature exceeds thermal shutdown limit. since the pin is open drain functionality, an external pull up resistor to vbat must be added (10 k minimum value). 11 out output output voltage pin. this pin follows in pins when ?no input fault? is detected. the output is disconnected from the v in power supply when the input voltage is under the uvlo threshold or above ovlo threshold or thermal shutdown limit is exceeded.in reverse mode, the device is supplied across out pin. 12 nc nc not connected 13 pad1 power the pad1 is used to dissipate the internal mosfet thermal energy and must be soldered to an isolated pcb area. the area mustn?t be connected to any other potential than complete isolated one. see pcb recommendations on page 9. maximum ratings rating symbol value unit minimum voltage (in to gnd) vmin in ? 30 v minimum voltage (all others to gnd) vmin ? 0.3 v maximum voltage (in to gnd) vmax in 30 v maximum voltage (out to gnd) vmax out 10 v maximum voltage (all others to gnd) vmax 7 v thermal resistance, junction ? to ? air, (note 1) r ja 200 c/w operating ambient temperature range t a ? 40 to +85 c storage temperature range t stg ? 65 to +150 c junction operating temperature t j 150 c esd withstand voltage (iec 61000 ? 4 ? 2) human body model (hbm), model = 2, (note 2) machine model (mm) model = b, (note 3) vesd 15kv air, 8kv contact 2000v 200v kv v v moisture sensitivity msl level 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the r ja is highly dependent on the pcb heat sink area (connected to pad1). see pcb recommendation paragraph. 2. human body model, 100 pf discharged through a 1.5 k resistor following specification jesd22/a114. 3. machine model, 200 pf discharged through all pins following specification jesd22/a115.
NCP370 http://onsemi.com 4 electrical characteristics (v in = 5 v, minimum/maximum limits at ? 40 c < t a < +85 c unless otherwise noted. typical values are at t a = +25 c) characteristics symbols conditions min typ max unit input voltage range v in disable, direct and enhance modes, v out = 0 v ? 28 28 v input voltage vin min disable, direct and enhance modes, v out = 4.25v ? 24 v output voltage range v out reverse mode 2.5 5.5 v undervoltage lockout threshold uvlo vin falls below uvlo threshold (disable, direct and enhance modes) 2.6 2.7 2.8 v undervoltage lockout hysteresis uvlo hyst v in rises above uvlo threshold + uvlo hyst 45 60 75 mv over voltage lockout threshold NCP370muaitxg ovlo v in rises above ovlo threshold (disable and direct modes) 6.3 6.6 6.9 v overvoltage lockout hysteresis ovlo hyst v in falls below to ovlo ? ovlo hyst 60 80 100 mv over system voltage lockout ovlo 00 v in rises above ovlo 00 threshold enhanced mode @ 25 c 7.9 8.27 8.6 v overvoltage lockout hysteresis ovlo 00hyst v in falls below to ovlo 00 ? ovlo 00hyst @ 25 c 80 100 145 mv v in to v out resistance r ds(on) v in = 5 v, direct mode, load connected to v out v in = 5 v, direct mode, load connected to v out @ 25 c 130 130 220 200 m v out to v in resistance r ds(on) v out = 5 v, reverse mode, accessory connected to v in v out = 5 v, reverse mode, accessory connected to v in @ 25 c 130 130 220 200 m input standby current idd std no load. disable mode, v in connected 140 200 a input supply quiescent current idd in no load. direct mode 200 280 a output standby current idd stdout rin = 10 k , v out = 5.5 v, disable mode 0.02 1.0 a reverse mode current idd rev no accessory, v out = 4.2 v, reverse mode 200 315 a minimum dc current i chg output load, v in = 5.5 v, direct 1.3 a i rev accessory, v out = 5.5 v, reverse modes 1.3 overcurrent threshold i ocp v out = 4.2 v, load on v in , reverse mode, r ilim = 0 , 1 a/1 s 1.35 1.75 2.10 a overcurrent response i acc direct accessory short, reverse mode, v out = 4.2 v, i lim = 1.6 a 7.0 % flag output low voltage vol flag 1.2 v < v in < uvlo sink 50 a on flag pin 30 400 mv v in > ovlo, sink 1 ma on flag pin 400 i reverse > i lim , sink 1 ma on flag pin 400 flag leakage current flag leak flag level = 5.5 v 1.0 na dir voltage high v ihdir 1.2 v dir voltage low v ildir 0.55 v dir leakage current dir leak v in or v out connected v in and v out disconnected 200 1.0 na rev voltage high v ihrev 1.2 v rev voltage low v ilrev 0.55 v rev leakage current rev leak v in or v out connected v in and v out disconnected 200 1.0 na thermal shutdown temperature t sd 150 c thermal shutdown hysteresis t sdhyst 30 c
NCP370 http://onsemi.com 5 characteristics unit max typ min conditions symbols timings direct mode start up delay t on from v in > uvlo to v out 0.3 v 20 30 40 ms flag going up delay t start from v out > 0.3 v to flag = 1.2 v 20 30 40 ms turn off delay t off from v in > ovlo to v out 0.3 v v in increasing from 5 v to 8 v at 3 v/ s 1.5 5.0 s alert delay t stop from v in > ovlo to flag 0.4 v see figure 3 and 9 v in increasing from 5 v to 8 v at 3 v/ s 1.5 s disable time t dis rev = 1.2 v, from dir = 0.4 v to 1.2 v to v out 0.3 v 2.5 s reverse mode reverse start up delay ton rev v out 2.5 v, from rev = 1.2 to 0.55 to v in 0.3 v, reverse mode 0.6 1.2 1.8 ms reverse flag going up delay tstart rev from v in 0.3 v flag = 1.2 v, reverse mode 0.6 1.2 1.8 ms rearming reverse delay t rrd v out > 2.5 v, r in = 1 , reverse mode 20 30 40 ms over current regulation time t reg v out > 2.6, v in > 0.3 v, reverse mode 0.5 1.2 1.8 ms ocp delay time t ocp from i reverse > i lim , 1 a/1 s 5 s reverse disable time t revdis from rev = 0.55 v to 1.2 v, to v in < 0.3 v. v out = 5 v 200 s note: electrical parameters are guaranteed by correlation across the full range of temperature. typical operating characteristics operation the NCP370 provides overvoltage protection for positive and negative voltages, up to 28 v or down to ? 28 v on in pins. at powerup, with dir pin = low, rev = high, the output rises 30 ms after the input rises above the uvlo. the NCP370 provides a flag output, which alerts the system that a fault has occurred. the flag signal rises 30 ms after the output signal rises. a reverse mode is available when an accessory is connected on in pins and the internal battery is applied on the out pin, allowing the accessory to be powered. in this mode, no supply must be connected on in pins and rev pin must be tied to low level. the NCP370 provides overcurrent protection for the battery from current faults in the accessory. undervoltage lockout (uvlo) to ensure proper turn ? on operation from ac/dc (or wall adapter charging) under any conditions, the device has a built ? in undervoltage lock out (uvlo) circuit. during positive going slope on v in , the output remains disconnected from input until v in voltage is above uvlo. the flag output will be low as long as v in has not reached uvlo threshold. this circuit has a 60 mv hysteresis to provide noise immunity to transient conditions. in reverse mode (rev pin 0.55 v, dir 1.2 v), uvlo and ovlo comparators are inactivated. overvoltage lockout (ovlo) to protect connected systems on vout pin from overvoltage, the device has a built ? in overvoltage lock out (ovlo) circuit. during overvoltage condition, the output is disabled as long as the input voltage exceeds ovlo. additional ovlo thresholds can be manufactured (please contact your on semiconductor representative for availability). flag output will be low since v in is higher than ovlo. this circuit has a 80 mv hysteresis to provide noise immunity to transient conditions . oversystem voltage lockout (ovlo 00 ) a second overvoltage comparator is available for supplying the sytem (output) by the w all adaptor (input) by setting dir = low and rev = low. the r ds(on) will be higher during this mode allowing to handle few 10 ma . this additional comparator allows to put higher input voltage (ovlo = 8.27 v typical) on the NCP370 during test production sequence (i.e: one time programming of the cell phone, pda). this parameter is 25 c guaranteed only. flag output the NCP370 provides a flag output which alerts that a fault has occurred. as soon as a fault state is detected by the NCP370 (see figure 3), the flag pin output goes low, alerting the micro ? controller to take appropriate action.
NCP370 http://onsemi.com 6 the flag pin goes low as soon the input voltage exceeds the ovlo threshold or falls below the uvlo threshold. when the v in level recovers normal condition, flag goes high after a time delay, t start (see figure 3 ), following the v out response. the flag pin is an open drain output and therefore a pull up resistor (typically 1 m , minimum 10 k ) must be connected to battery. the flag level will always reflect v in status, even if the device is turned off (dir = 1 and rev = 1). rev dir flag v out v in ovlo uvlo > 1.2 v t on t start t off t stop t on t start t dis figure 3. flag pin in ac/dc charging mode during over thermal condition (t j >t sd ), output is disconnected from input, and flag pin goes low. in reverse mode, flag pin remains available, allowing the micro ? controller to appropriately process the overvoltage condition, overcurrent condition or thermal shutdown condition.
NCP370 http://onsemi.com 7 figure 4. flag status in reverse mode v in rev dir flag v out battery output micro ? controller micro ? controller external accessory id = 1 ton rev table 1. flag table dir rev in out flag status pass element (dual nmos fet) 0 0 1.5 < v in < uvlo or v in > ovlo oo hiz low open 0 0 uvlo < v in < ovlo oo = v in ? dropout high close 0 1 1.5 < v in < uvlo or v in > ovlo hiz low open 0 1 uvlo < v in < ovlo = v in ? dropout high close 1 0 = v out ? dropout v out > 2.5 v high close 1 1 1.5 < v in < uvlo or v in > ovlo hiz low open 1 1 uvlo < v in < ovlo hiz high open dir input to enable direct charge operation (direct mode), the dir pin shall be forced to low and rev to high. a high level on the dir pin disconnects out pin from in pin. dir does not over ? ride an ovlo or uvlo fault (flag status is still available). table 2. table selection of charge modes dir rev mode 0 0 enhance mode 0 1 direct mode 1 0 reverse mode 1 1 disable mode
NCP370 http://onsemi.com 8 negative voltage and reverse current. the device protects the downstream side from negative voltage occurring on the in pin, down to ? 28 v. when a negative voltage occurs, the output is disconnected from the in pins. reverse mode in reverse mode, an external accessory plugged into the bottom connector can be powered by the internal battery of the system. to access to the reverse mode, dir pin must be tied high (> 1.2) and rev must be tied high to low (< 0.55 v). in this case, the core of the NCP370 will be supplied by the battery, with a 2.5 v minimum voltage and 5.5 v maximum voltage. in this reverse state, both ocp and thermal modes are available. overcurrent protection (ocp) this device integrates the reverse over current protection function, from battery to external accessory. that means the current across the internal nmos is limited when the value, set by the external r limit resistor, exceeds i ocp . an internal resistor is placed in series with the i lim pin allowing a maximum ocp value when i lim pin is directly connected to gnd. by adding external resistors in series from i lim to gnd, the ocp value is lowered. the typical overcurrent threshold can be calculated with the following formula; r ilim (k ) = (60 / i ocp ) ? 36 figure 5. reverse mode overcurrent protection vs. ilim resistance, r limit during an overcurrent event, the n ? mosfets turn off and flag output goes low, allowing the micro ? controller to process the fault event and then disable reverse charge path.
NCP370 http://onsemi.com 9 at power up (accessory is plugged on input pins), the current is limited up to i lim for 1.2 ms (typical), to allow capacitor charge and limit inrush current. if the i lim threshold is exceeded over 1.2 ms, the device enters ocp burst mode until the overcurrent event disappears. after 1 ms following the plug in of the accessory, the ocp mode is engaged. see figure 6. tstart rev figure 6. overcurrent protection sequence v in rev dir flag v out i lim drive current in accessory id i rev accessory id detection t reg t rrd ton rev thermal shutdown protection in case of internal overheating, the integrated thermal shutdown protection turns off the internal mosfets in order to instantaneously decrease the device temperature. the thermal threshold has been set at 150 c flag then goes low to inform the mcu. as the thermal hysteresis is 30 c, the mosfets will turn on as soon the device temperature falls below 120 c. if the fault event is still present, the temperature increase engages the thermal shutdown again until the fault event disappears. pcb recommendations since the NCP370 integrates the 1. 3a n ? mosfets, pcb rules must be respected to properly evacuate the heat out of the silicon. from an applications standpoint, pad1 of the NCP370 package should be connected to an isolated pcb area to increase the heat transfer if necessary. in any case, pad1 should be not connected to any other potential or gnd other than the isolated extra copper surface. to assist in the design of the transfer plane connected to pad1, figure 7 shows the copper area required with respect to r ja .
NCP370 http://onsemi.com 10 figure 7. copper heat spread area 0 50 100 150 200 250 0 100 200 300 400 500 600 700 0.5 1 1.5 2 2.5 0 power curve with pcb cu thk 1 oz power curve with pcb cu thk 2 oz ja curve with pcb cu thk 2 oz ja curve with pcb cu thk 1 oz copper heat spread area (mm 2 ) maximum ta ( c/w) esd tests the NCP370 conforms to the iec61000 ? 4 ? 2, level 4 on the input pin. a 1 f (i.e murata grm188r61e105ka12d) must be placed close to the in pins. if the iec61000 ? 4 ? 2 is not a requirement, a 100 nf/25 v must be placed between in and gnd. the above configuration supports 15 kv (air) and 8 kv (contact) at the input per iec61000 ? 4 ? 2 (level 4). please refer to figure 8 for the iec61000 ? 4 ? 2 electrostatic discharge waveform. figure 8. i peak = f(t)/iec61000 ? 4 ? 2 r ds(on) and dropout the NCP370 includes two internal low r ds(on) n ? mosfets to protect the system, connected on out pin, from overvoltage, negative voltage and reverse current protection. during normal operation, the r ds(on) characteristics of the n ? mosfets give rise to low losses on v out pin. as example: r load = 8 , vin= 5 v. r ds(on) = 155 m . i out = 800 ma. v out = 4.905 v nmos losses = r ds(on) x i out 2 = 0.155 x 0.8 2 = 0.0992 w
NCP370 http://onsemi.com 11 package dimensions llga12 3x3, 0.5p case 513ak ? 01 issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ??? ??? ??? a d e b c 0.15 pin one 2x reference 2x top view side view bottom view a l d2 e2 c c 0.15 c 0.10 c 0.08 12x a1 seating plane e 12x note 3 b 12x 0.10 c 0.05 c a b b dim min max millimeters a 0.50 0.60 a1 0.00 0.05 b 0.20 0.30 d 3.00 bsc d2 2.60 2.80 e 3.00 bsc e2 1.90 2.10 e 0.50 bsc k 0.20 ??? l 0.25 0.35 1 6 12 7 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 12x 0.43 3.30 0.50 pitch 2.05 0.50 2.75 1 k 12x dimensions: millimeters 0.30 11x on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scill c and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP370/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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